Single-crystal semiconductor devices and method for making them

ABSTRACT

A large, single-crystal semiconductor device is made from a substrate having a layer of polycrystalline or amorphous material thereon by exposing a region of the layer to a beam of electrons to melt the region and then solidifying the molten region from one end to the other in a first direction and outwardly toward the edges in a second direction normal to the first direction to form a single-crystal seed in the region. An operating layer of polycrystalline or amorphous material on the substrate in contact with the seed is scanned with a beam of electrons having a strip-like configuration. The beam remelts a portion of the seed and creates a molten zone in the layer that recrystallizes as a single crystal by lateral epitaxial recrystallization from the seed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor devices and, moreparticularly, to large, single-crystal semiconductor devices and methodsfor making such devices.

2. Description of the Prior Art

The use of a high-energy beam for growing a large single crystal from alayer of polycrystalline material on a substrate has been proposed. Asthe beam scans the substrate it melts the layer and, ideally, when themolten zone cools it solidifies into a single crystal.

One of the conditions required to convert the polycrystalline layer intoa single crystal is the provision of a "seed"; that is, a single crystalwhich is in contact with the molten zone to cause it to solidify as asingle crystal. There has not yet been proposed any completelysatisfactory means of producing such a seed.

Various conventional energy sources, such as spot laser beam, spotelectron beam, graphite strip heater and arc strip lamp, have beenproposed for use in melting the polycrystalline layer to induce liquidor solid phase regrowth by epitaxial recrystallization.

However, such conventional energy sources are unsatisfactory. Forexample, spot beam energy sources produce a resulting recrystallizedlayer lacking a uniform single-crystalline structure. Conventional stripbeam energy sources, such as graphite strip heaters and arc strip lamps,can damage the underlying substrate because they require a relativelylong time of contact of the beam with the polycrystalline layer, whichresults in dissipation of an unacceptable amount of heat from the layerinto the underlying substrate.

Such energy sources are also unsuitable for producing a single seedcrystal. A spot laser or electron beam, impinging momentarily on apolycrystalline layer, will create a relatively small, circular moltenregion in the layer. However, when the region solidifies, its boundarywith the rest of the layer contains small silicon crystals, which ofcourse make the region unsuitable for use as a seed. Scanning the layerwith a spot beam has also not provided a suitable seed. And theconventional strip energy sources are unsatisfactory for the same reasonthat they cannot be used for growing a single-crystal layer.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a single-crystalsemiconductor device that overcomes the shortcomings of the prior art.

It is another object of the present invention to provide a method ofmaking a single-crystal semiconductor device using a seed crystal formedin a polycrystalline or amorphous layer on a substrate and then meltinga polycrystalline or amorphous layer in contact with the seed to causeepitaxial recrystallization of the layer.

In accordance with an aspect of the present invention a method isprovided of making a large, single-crystal semiconductor devicecomprising the steps of providing a wafer including a substrate havingthereon a seed layer of polycrystalline or amorphous material, exposinga region of the layer to a beam of electrons to melt the region, coolingthe molten region so that solidification thereof proceeds along a firstdirection and outwardly toward the edges of the region in a seconddirection substantially normal to the first direction for forming asingle-crystal seed in the region, and scanning the layer with a beam ofelectrons having a strip-like configuration to remelt a portion of theseed and to create a molten zone in the layer that recrystallizes as asingle crystal to lateral epitaxial recrystallization from the seed.

Those and other objects, features and advantages of the presentinvention will become apparent when the following detailed descriptionof preferred embodiments of the invention is considered with thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view of a wafer schematically illustrating in principlethe provision of a region in which a seed crystal is formed in apolycrystalline or amorphous layer on a substrate.

FIG. 2 is a side elevation view of the wafer shown in FIG. 1.

FIG. 3 is a plot of the temperature gradient in the region shown in FIG.1 in a first direction at any given time during the resolidification ofthe region after it has been melted.

FIG. 4 is a plot of the temperature gradient in the region shown in FIG.1 in a second direction at any given time during the resolidification ofthe region after it has been melted.

FIG. 5 shows the directions of resolidification of the molten region.

FIG. 6 illustrates one temperature gradient over time in the regionshown in FIG. 1 in the first direction.

FIG. 7 illustrates another temperature gradient over time in the regionshown in FIG. 1 in the first direction.

FIG. 8 illustrates one temperature gradient over time in the regionshown in FIG. 1 in the second direction.

FIG. 9 illustrates another temperature gradient over time in the regionshown in FIG. 1 in the second direction.

FIGS. 10 and 11 illustrate apparatus for providing a strip-like electonbeam for melting the region shown in FIG. 1.

FIGS. 12-15 illustrate apparatus for providing the initial temperaturegradient shown in FIG. 6.

FIGS. 16-21 illustrate apparatus for providing the initial temperaturegradient shown in FIG. 8.

FIGS. 22-28 illustrate wafer constructions for providing thetemperature-time relationship shown in FIG. 7.

FIGS. 29-31 illustrate wafer constructions for providing thetemperature-time relationship shown in FIG. 9.

FIGS. 32-33 illustrate an alternate embodiment of the waferconstructions shown in FIGS. 22-31.

FIGS. 34-38 illustrate a method of making a single-crystal semiconductorlayer using the seed formed on the wafer shown in FIG. 30.

FIG. 39 illustrates a wafer construction for making a single-crystalsemiconductor layer.

FIG. 40 is a top view of a wafer like that shown in FIG. 1 with aplurality of seeds formed thereon.

FIG. 41 illustrates a possible temperature profile in thepolycrystalline layer of a wafer like that shown in FIG. 1.

FIG. 42 illustrates another possible temperature profile in thepolycrystalline layer of a wafer like that shown in FIG. 1.

FIG. 43 is a top view of part of a wafer like that shown in FIG. 1showing the temperature distribution created in the seed region by theembodiments shown in FIGS. 41-42.

FIG. 44 is a top view of an alternate wafer construction for making aplurality of single-crystal seeds.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIGS. 1 and 2 show a wafer 100 from the top and in elevation,respectively. The wafer 100 comprises a circular substrate 102 about 3inches in diameter having a layer 104 of polycrystalline or amorphousmaterial on it about 0.5 to 1.0 microns thick. By "polycrystalline" ismeant a material comprising a large number of relatively small crystals.A typical example is polysilicon, which will be used herein to describethe present invention. However, by using polysilicon to describe thefeatures of the present invention it is not intended to limit the kindsof materials suitable for use as the polycrystalline or amorphous layer104.

The layer 104 of polysilicon is deposited on the substrate 102 by amethod such as chemical vapour deposition ("CVD"). In the presentinvention, the substrate 102 can be any almost any material thatpresents a smooth surface, a feature which forms one of the advantagesof the present invention, as will be appreciated from this description.Examples of materials suitable as a base for the substrate 102 areglass, quartz, sapphire and a crystalline semiconductor materials suchas silicon, germanium or gallium arsenide. The base can also be asingle-crystal semiconductor material with semiconductor-device regionsformed therein. The use of such a base is particularly advantageousbecause the present invention will enable a three-dimensional device tobe constructed on the base. In any case, the polysilicon layer 104 is tobe deposited on an underlying insulating layer, so that if the base ofthe substrate 102 is not an insulating material, then a layer (not shownin FIG. 1) of an insulating material such as SiO₂ or silicon nitride isused underneath the layer 104.

A seed comprising a single crystal of silicon is formed in the layer 104of polysilicon by heating a region 106 of the layer 104 of polysiliconto above its melting point and then cooling the molten region undercontrolled conditions. Those conditions can be defined by establishing acoordinate system having "x" and "y" axes as shown in FIG. 1. To form asingle-crystal seed the region 106 of polysilicon is heated to above themelting point of silicon, for example, to about 1410° C., and thencooled to establish the temperature gradients shown in FIGS. 3 and 4 atany particular time during cooling . "T_(melt) " indicates the meltingpoint of silicon. At any given time the temperature gradient (in °C. percm) across the solid-liquid interface in a given direction in thesolidifying region should have a minimum value which depends on thesolidification speed in that direction and the material. For example,for polysilicon, the temperature gradient in °C. per centimeter shouldbe at least 5000 times the solidification speed in centimeters persecond.

FIG. 5 illustrates how those temperature gradients create a singlecrystal from the molten region 106. As the region 106 cools, the moltensilicon solidifies in the directions shown by the arrows 108, 110 and112. Solidification of the region 106 proceeds along a first directionshown by the arrow 108 and outwardly toward the edges, as shown by thearrows 110 and 112, in a second direction normal to the first direction.This cooling pattern converts virtually the entire region 106 into asingle crystal, with the exception of a small portion 114 at one end.

FIGS. 6-9 illustrate how that cooling pattern can be created. FIGS. 6and 7 show the creation of a temperature distribution in the firstdirection (that is, in the y-direction as seen in FIG. 1).

In the embodiment illustrated in FIG. 6, the region 106 is initiallyheated so that it exhibits the increasing temperature gradient shown inFIG. 6. The region 106 then cools uniformly along its length (in they-direction) and, as each location in the region 106 cools below themelting point of silicon, it solidifies. At time t₁, for example, theregion 106 at y₁ solidifies; at time t₂, the region 106 at y₂solidifies, and so on. Thus, the region 106 solidifies in the directionof the arrow 108 in FIG. 5.

Alternatively, the region 106 can initially be heated to a uniformtemperature as shown in FIG. 7. In this embodiment the temperaturedistribution is established as the region 106 cools. The solidificationdirection is established by the non-uniform cooling pattern graphicallyillustrated in FIG. 7, in which the locations y₁, y₂, y₃, etc., solidifyat times t₁, t₂, t₃, etc., respectively, similar to the embodiment shownin FIG. 6.

FIGS. 8 and 9 show how the proper temperature distribution can beestablished across the region 106 in the second direction (that is,along the x-axis). As shown in FIG. 8, the region 106 can be initiallyheated to establish the temperature gradient shown as T_(initial). Then,as the zone 106 cools, the locations x₁, x₂ and x₃ solidify at times t₁,t₂ and t₃, respectively, Hence, the direction of solidification, asshown graphically in FIG. 8, is in the direction of the arrows 110 and112 in FIG. 5.

Alternatively, the region 106 can be initially heated to a uniformtemperature as shown in FIG. 9, and then cooled non-uniformly. In thatcase, solidification proceeds as is graphically shown in FIG. 9, whichalso corresponds to the direction of the arrows 110 and 112 in FIG. 5.

The creation of a molten region in the layer 104 requires the deposit ofa large amount of energy in the layer. That can be accomplished by usingthe fine-line electron beam disclosed in co-pending U.S. patentapplication Ser. No. 455,266, filed Jan. 3, 1983, now U.S. Pat. No.4,446,373, issued on May 1, 1980 as a continuation of patent applicationSer. No. 224,313, now U.S. Pat. No. 4,382,186, U.S. Pat. No. 4,382,186has been disclaimed in favor of U.S. Pat. No. 4,446,373, and assigned tothe assignee of the present invention.

As disclosed in that application, such an electron beam can be generatedusing the apparatus 140 shown in FIGS. 10 and 11. The apparatus 140creates a strip electron beam B that can deposit electrons with kineticenergies, power densities and energy densities having levels which melta surface region of a workpiece, here the wafer 100, quickly enough toprevent heat conduction to the substrate underlying the surface region.

The apparatus 140 consists of a strip-like thermionic cathode 141 whichis disposed in an evacuated housing 142 and is heated to releaseelectrons. An extraction grid 144 controls the electrons and injectsthem to a focussing aperture 146. The electrons then pass through aground aperture 148. A deflection system comprises electrostatic plates150 across which a deflection voltage DV is applied. A potentialdifference V is maintained between the substrate 100 and the cathode 141and a control system C can be provided to control the extraction gridvoltage.

FIG. 11 shows schematically the shape of the electron beam B.

In this embodiment, the electron beam B momentarily impinges, forbetween 10 and 1000 microseconds, on the layer 104 initially to melt theentire region 106, which is then left to cool and solidify as describedabove in connection with FIGS. 6-9.

FIGS. 12-15 illustrate embodiments in which the region 106 is initiallyheated with the proper temperature gradient in the y- or firstdirection, as described above in connection with FIG. 6.

In FIG. 12 the cathode 141 is heated non-uniformly along its length by aplurality of resistance heaters 160A, 160B, 160C, 160D, 160E and 160F.If the current supplied to each heater is slightly larger than thatsupplied to the immediately preceeding heater, then the current densityof the beam B varies along the y-axis and the region 106 is heatednon-uniformly along its length.

In FIG. 13 the cathode 141 is heated uniformly along its length, but theextraction grid elements 144A and 144B have applied thereto a potentialgradient in the first direction. Thus the electron beam B has a highercurrent density at one end and heats the region 106 with the temperaturegradient shown in FIG. 6.

In FIG. 14 the cathode 141 is heated uniformly along its length and theextraction grid elements 144A and 144B have a uniform potential alongtheir length. However, motors 162A and 162B are used to vary thedistance between the elements 144A and 144B by rotating the elementsabout axes 164A and 164B, respectively. Again, the effect is to providean initial temperature gradient like that in FIG. 6 in the region 106.

FIG. 15 shows another embodiment in which the cathode C is uniformlyheated. A motor 166 is used to change the angular orientation of thewafer 100 relative to the cathode 141 to create the temperature gradientshown in FIG. 6.

FIGS. 16-21 illustrate embodiments by which the region 106 can beinitially heated with the lateral temperature distribution in the x- orsecond direction described above in connection with FIG. 8.

In FIG. 16, a conductive element 168 is placed underneath the cathode141 to extend along its length in the first direction. The element 168is midway between the edges of the cathode 141 in the second direction.The potential of the element 168 relative to the wafer 100 is less thanthe potential of the cathode 141 so that the current density of the beamB increases from the center to the edges and creates the temperaturegradient shown in FIG. 8.

FIG. 17 shows an arrangement using two cathodes 141₁ and 141₂. Byproviding an angle A between the cathodes, the current density of thebeam B can be controlled to provide the temperature gradient shown inFIG. 8.

FIG. 18 shows a modified cathode 141'. The cathode 141' has a curvedemitting surface 170 which creates a beam B having a current density atthe substrate that creates a temperature gradient like that shown inFIG. 8.

FIG. 19 shows the cathode 141 heated internally by two filaments 172 and174. The use of two spaced-apart filaments creates a current densitygradient in the electron beam B which creates a temperature distributionin the region 106 like that shown in FIG. 8.

FIG. 20 shows a slight modification of the embodiment shown in FIG. 19.The cathode 141 in this embodiment comprises two cathode elements 141Aand 141B which have the filaments 172 and 174 embedded therein,respectively. The cathode elements 141A and 141B are separated by aninsulating member 176. When the filaments 172 and 174 are heated by thepassage of current therethrough, the cathode elements 141A and 141Bcreate a beam B the current density of which at the wafer surfaceestablishes the temperature distribution shown in FIG. 8.

In the embodiment of FIG. 21, the cathode 141 is coated with two areas178 of material, for example, Ba₂ O with cesium, having a higheremissivity of electrons than the material of the cathode 141. When thecathode 141 is heated the areas 178 emit more electrons and create thetemperature distribution shown in FIG. 8.

Of course, to create both temperature gradients shown in FIGS. 6 and 8,any of the embodiments in FIGS. 12-15 can be combined with any of theembodiments in FIGS. 16-21. For example, the cathode shown in FIG. 21could be heated along its length as shown in FIG. 12 to create thelongitudinal and lateral temperature gradients shown in FIGS. 6 and 8,respectively.

It is also possible initially to create a uniform temperature in theregion 106 and control the manner in which it cools non-uniformly toprovide solidification in the proper directions as described above inconnection with FIGS. 7 and 9.

FIGS. 22-24 illustrate a wafer provided with a structure that createsthe temperature gradient over time shown in FIG. 7 as the region 106cools. The substrate 102 includes a thermal layer 200 on which isprovided the region 106 of polysilicon. The thermal layer 200 providesdifferent rates of heat conduction in different areas thereof. Thethermal layer 200 comprises a first layer 202 of a good heat conductorsuch as polysilicon deposited by any well-known method such as CVD. Ontop of the first layer 202 a second layer 203 of a heat-insulatingmaterial such as SiO₂ is formed by CVD. The second layer 203 is maskedand etched by well-known techniques to form a fence 204 that defines theregion 106. At one end of the region 106 a portion 206 of the secondlayer 203 is etched to a slightly greater depth than the remainder ofthe region 106. Polysilicon is then deposited in the region 106 boundedby the fence 204.

When the substrate 102 shown in FIGS. 22-24 is subjected to the electronbeam, it is initially heated throughout, say to an even temperature asshown in FIG. 7. However, as it cools the portion 206 forms a heat sinkbecause of the reduced thickness of the second layer of heat-insulatingmaterial 203. Furthermore, the fence 204 retards heat flow from themolten polysilicon in the region 106 in directions other than throughthe portion 206. Thus, the region 106 cools as shown in FIG. 7 andsolidifies in the direction of the arrow 108 shown in FIG. 5.

In an alternate embodiment, the second layer 203 is changed slightly asshown in FIG. 25. In this embodiment, the thickness of the layer 203Agradually increases from one end of the region 106 to the other. Whenthe region 106 of polysilicon is exposed to a uniform electron beam, itmelts and then solidifies again as shown in FIGS. 5 and 7.

In still another embodiment, as shown in FIG. 26, the second layer 203is substantially as shown in FIG. 24. However, the effect of the heatsink action of the portion 206 is enhanced by providing aheat-conducting radiator 210 in contact with the polysilicon in theregion 206. The radiator 210 conducts heat from the end of the zone 208and radiates it into the ambient surroundings to enhance the coolingpattern provided by the wafer shown in FIG. 24.

It is also possible to enhance the cooling pattern described inconnection with FIG. 7 by preventing exposure of certain parts of thezone to the electron beam B. As shown in FIG. 27, a substrate 102 isprovided with the layers 202 and 203 substantially as shown in FIG. 24.A mask 212 is disposed above the heat sink formed by thereduced-thickness portion 206 to prevent the extreme end of the region106 from being exposed to the electron beam B. Thus, a relatively coolerregion is provided which enhances the heat flow and provides the coolingpattern illustrated in FIG. 7.

FIG. 28 shows a slight modification of the embodiment shown in FIG. 27,in which a mask is also used as a radiator, similar to the radiator 210shown in FIG. 26. In FIG. 28 the radiator 212' masks some of thepolysilicon in the region 106 from exposure to electrons. In addition,because it is in contact with the polysilicon in the region 106, it alsoacts as a radiator further to enhance the required cooling pattern.

It is also possible to construct a wafer that controls the manner inwhich the region cools laterally (in the second or x-direction) asdescribed above in connection with FIG. 9. FIGS. 29-31 describe indetail such a wafer construction.

In FIG. 29 the substrate 102 includes a thermal layer 200' deposited onthe base of the substrate and comprising a first layer 202' of aheat-conducting material and a second layer 203' of a heat-insulatingmaterial. As described above in connection with FIGS. 24-26, the layer202' will typically consist of polysilicon. After deposition, that layeris etched to form a small ridge 214 running in the y-direction as shownin FIG. 29. On top of the first layer 202' of polysilicon, the secondlayer 203' of heat-insulating material, such as SiO₂, is formed and thenetched to provide the cross-section shown in FIG. 29. More particularly,the second layer 203' is etched to provide the fence 204 around theregion 106 and a central portion 216 overlying the ridge 214 and havinga reduced thickness. The layer of polysilicon which will form the seedcrystal is deposited in the region 106. The substrate 102 is thensubjected to a uniform electron beam which heats it above its meltingpoint. As the molten polysilicon in the region 106 cools, a temperaturegradient is established as described in connection with FIG. 9, so thatthe direction of solification proceeds as shown in FIG. 5. The reducedthickness portion of the layer 203' in the middle of the region 106 actsas a heat sink to establish the proper temperature gradient in thecooling polysilicon.

In FIG. 30, a slightly altered embodiment of the configuration shown inFIG. 29 is illustrated. In constructing the wafer shown in FIG. 30, thestep of etching the first layer 202' of polysilicon is omitted. Thus, auniform layer 202 of polysilicon, like that shown in FIGS. 24-26, isdisposed on the substrate 102 beneath the etched layer 203' of SiO₂.When the region 106 of polysilicon is melted by the uniform electronbeam, the reduced thickness area 216' in the center of the region 106acts as a heat sink, like that described in connection with FIG. 29.

In FIG. 31 another embodiment is shown. The substrate 102 and the firstlayer 202 are substantially identical to those described in connectionwith FIG. 30. However, the layer of insulating material is etched toprovide a second layer 203" with the cross-section shown in FIG. 31.Thus, when the region 106 is subjected to a uniform electrical beam, andinitially heated as shown in FIG. 9, it will cool and solidify as shownin FIG. 5.

FIGS. 32 and 33 show another embodiment for establishing the coolingpatterns shown in FIG. 5. A substrate 102 is provided with the thermallayer 200 (not identified by reference numeral in FIGS. 32 and 33);comprising a first layer 202 of polysilicon and a second layer 203 ofSiO₂ substantially as has already been described. Within the fence 204 aheating member 218, made of a material which absorbs electrons and isheated thereby, surrounds the periphery of the region 106. This member218 typically is made of a material with properties such that theparameter kρC (where k=thermal conductivity in watts/cm-°C., ρ=densityin g/cm³ and C=specific heat in Joules/g-°C.), is relatively low, saybelow 1.0, which is the value of kρC for silicon. A typical example ofsuch a material is titanium, which has a value of kρC=0.2.Qualitatively, the parameter kρC can be regarded as a measure of howreadily a material will heat when exposed to energy, with materialswhich heat more readily exhibiting smaller values for kρC. When theregion 106 is subjected to the electron beam, the heating member 218 isheated and the heat thereof is retained because of the insulatingcharacteristics of the fence 204. Thus, the cooling pattern shown inFIG. 5 is further enhanced.

Thus, a single crystal can be formed on a relatively inexpensivesubstrate material. Those skilled in the art will recognize that theembodiments thus far disclosed can be used in almost any combination toprovide the solidification pattern shown in FIG. 5. For example, anelectron beam which creates an initial temperature gradient can be usedwith a wafer configuration which enhances solidification in thenecessary directions, or the wafer construction can be used to create acooling pattern in one direction while the apparatus used to provide theelectron beam alone creates the necessary cooling pattern in the otherdirection.

The single crystal thus is particularly adapted to be used as a seed formaking a large, single-crystal semiconductor device by scanning with thestrip-like electron beam B as shown in U.S. patent application Ser. No.492,800, filed May 9, 1983, and assigned to the assignee of the presentinvention. Thus, it is particularly convenient to use the same type ofelectron beam to melt the region 106, which results in an elongatedrectangular seed, as shown herein. However, those skilled in the artwill recognize that other seed-crystal shapes are possible.

After a seed has been formed, the same or a similar electron beam isused to scan the wafer to form a large, single-crystal semiconductordevice in accordance with the disclosure in the aforementioned patentapplication. In particular, FIG. 34 shows schematically the use of theelectron beam B to scan the surface of the wafer 100. The beam B beginsat a location such that it melts some but not all of the single-crystalseed in the region 106 and then is moved relative to the wafer 100 tocreate a molten zone in a polysilicon layer on the substrate which growsinto a single crystal from the seed. As shown in FIG. 34, the portion114 of the seed is not usable and generally is etched off the substratebefore it is scanned by the electron beam to create the semiconductordevice.

FIGS. 35-38 illustrate in detail how the seed can be used to create alarge, single-crystal semiconductor device.

FIG. 35 shows a wafer 100 having a cross-section similar to that shownFIG. 30. The layer 220 of polysilicon which is used to form the seed isgenerally deposited over the entire surface of the subtrate prior tocreating the seed, a detail which was omitted from the description abovefor the sake of clarity. That approach saves the manufacturing expenseand time which would be required to mask those areas of the surface ofthe substrate which were not going to be used to form the seed. In anycase, FIG. 35 shows the wafer 100 after the seed has been formed in theregion 106.

FIG. 36 shows a chemical-resist mask 300 which is deposited over thesurface of the wafer and then etched to expose one side of the fence 204and the portion of the layer 220 of the polysilicon which was not formedinto the seed by the electron beam B. In FIG. 37, the wafer 100 is shownafter the layer 220 of polysilicon and one side of the fence 204 hasbeen removed by etching and after the chemical-resist mask 300 has beenremoved. An operating layer of polysilicon 302 is then depositedpartially on the seed as shown in FIG. 38 by conventional techniques.The wafer 100 in FIG. 38 can then be scanned by the electron beam B asillustrated in FIG. 34 to form a large single-crystal semiconductordevice by lateral epitaxial recrystallization of the operating layer.

FIG. 39 illustrates a wafer configuration that enhances the tendency ofthe molten polysilicon, created when the layer 302 is scanned by theelectron beam B, to solidify in the proper direction.

As discussed in patent application Ser. No. 492,800, the direction ofsolidification of the molten polysilicon must be controlled if a goodquality, single-crystal layer is to be provided. Specifically,solidification should proceed in the same direction for the entireregion in which the single crystal is to be provided. The constructionshown in FIGS. 35-38 conveniently provides for enhancing the tendency ofthe polysilicon to solidify in the same direction because of the heatsink provided to form the crystal. By using the same techniques informing the large single-crystal device that were used in forming theseed, that tendency can be further enhanced.

As shown in FIG. 39, the wafer 100 shown in FIG. 38 can be prepared witha fence 204 of SiO₂ around the layer 302 of polysilicon that will formthe single crystal when scanned by the electron beam B. (Depiction ofthe edges of the seed S and the layer 302, which are shown in FIG. 38,has been omitted from FIG. 39 for clarity.) The reduced thicknessportion 216' will thus provide a heat sink while the fence 204' retardsheat flow from the remainer of the region.

Those skilled in the art will recognize that any of the configurationsshown in FIGS. 29-31 will provide a heat sink when the layer 302 ofpolysilicon is scanned to produce a large single-crystal. In addition,the use of a heating member like that shown in FIGS. 32-33 can also beused to provide the desired direction of heat flow in the moltenpolysilicon area.

Those skilled in the art will realize that it might be desirable toprovide more than one seeding location in the path of the electron beamB as it scans the wafer surface. It will be readily recognized that itis possible to provide as many such seeds across the wafer surface asare deemed necessary and provide them with the proper spacing as well.For example, the cross-section shown in FIGS. 29-31 can be repeated asmany times as are desired on the surface of the substrate to providemultiple seeding locations on the wafer shown in FIGS. 34-38.

Thus a large, single-crystal semiconductor device can be provided on arelatively inexpensive substrate material because the substrate is notthe source of the seed, as in the technique described in patentapplication Ser. No. 492,800. In addition, because the depth of themolten zone can be precisely controlled using the electron beamdisclosed herein, it is possible to create a seed in only the upperportion of the polysilicon layer on the substrate and then also to forma single crystal in only an upper portion of the polysilicon layer.Using that technique, a single-crystal device can be created directly ontop of a layer of polysilicon.

FIG. 40 illustrates the use of the electron beam B to scan a substrateto form a plurality of seeds S. For example, assume that the wafer 100was provided with a plurality of regions 106 having the cross-sectionshown in either FIG. 29, 30 or 31. The electron beam B is then used toscan the wafer as shown in FIG. 40. The proper direction ofsolidification in the first direction is established by the scanningbeam as discussed in patent application Ser. No. 492,800. Thetemperature distribution in the second direction, across the region 106,is established as discussed above in connection with FIGS. 29-31. Thus,a plurality of seeds S can be formed in one continuous process.

In a variation on this embodiment, shown in FIGS. 41 and 42, theelectron beam intensity is varied along the length or width of thecathode, respectively. The wafer 100 with a single uniform layer ofpolysilicon, as shown in FIG. 2 for example, is scanned using such anelectron beam B. A plurality of alternating hot and cool zones areformed on the surface of the substrate as shown in FIG. 43. Theresulting solidification pattern corresponds to that shown in FIG. 5 andthus a plurality of seeds can be formed without using the variousconfigurations of fences, heat sinks and masks discussed above. Ofcourse the temperature profile shown in FIG. 41 can be repeated manytimes across the length of the cathode to form a plurality of seeds asthe beam scans the wafer. In addition, by turning the beam on and off, apattern of seeds like that shown in FIG. 40 can be created.

Those skilled in the art will recognize from FIGS. 10-21 how toconstruct apparatus for providing an electron beam for providing thetemperature pattern shown in FIGS. 41 and 42. For example, the electronbeam depicted in FIG. 42 can be provided by any of the configurationsdiscussed above and shown in FIGS. 16-21.

FIG. 44 illustrates in particular how the general principles thusdescribed can be used to form seeds having any desired configuration. Asshown in FIG. 43, the wafer 100 has a thermal layer with a cross-sectionsimilar to that shown in FIG. 24, for example. A plurality of regions106 are provided adjacent to and spaced from each other and a commonheat sink is provided in the area 206 having a reduced thicknessinsulating layer. As the electron beam B scans the wafer, a seed isformed in each region 106. The long dimensions of the beam moves normalto the regions 106 for forming the seeds and, to produce the finaldevice, the beam scans the wafer with its long dimension parallel to theseeds formed in the regions 106.

The formation of the seeds can be enhanced by not turning on theelectron beam until part of the region 206 has been traversed, whichwill make the region 206 even cooler and promote heat flow in the properdirection.

The advantages of the present invention will be apparent to thoseskilled in the art. A large, single-crystal semiconductor device or aplurality of such devices having almost any desired configuration can beeasily and quickly made on virtually any substrate material. The expenseboth in terms of material costs and yields of large, single-crystalsemiconductor devices can be significantly increased by using thepresent invention.

The present invention has been described by referring to many particularembodiments. However, those skilled in the art will recognize thatnumerous modifications other than those specifically pointed out can bemade without departing from the spirit of the invention. For thatreason, the scope of present invention is limited and defined solely bythe following claims.

What is claimed is:
 1. A method of making a large, single-crystalsemiconductor article, comprising the steps of:providing a waferincluding a substrate having thereon a seed layer of polycrystalline oramorphous material; exposing a region of said seed layer to a beam ofelectrons to melt said region; solidifying said molten region from oneend of said region in a first direction and outwardly toward the edgesof said region in a second direction substantially normal to said firstdirection for forming a seed comprising substantially a single crystalin said region; and scanning an operating layer of polycrystalline oramorphous material on said substrate in contact with said seed with abeam of electrons having a strip-like configuration by moving said waferand said beam relative to each other in said second direction to remelta portion of said seed and to create a molten zone in said operatinglayer that recrystallizes substantially as a single crystal by lateralepitaxial recrystallization from said seed.
 2. A method as in claim 1;comprising the step of providing a substrate base and a thermal layer onsaid substrate base including a heat-insulating layer underlying saidregion and forming a fence enclosing said region and further comprisingthe steps of:removing from one side of said region said fence extendingin said first direction after said seed is formed; and providing saidoperating layer as a substantially continuous layer of polycrystallineor amorphous material in contact with said one side of said region.
 3. Amethod as in claim 2; wherein said seed layer substantially covers saidsubstrate, the method further comprising the steps of:depositing a maskon said seed and leaving exposed the remainder of said seed layer andone side of said fence; removing said remainder of said seed layer andsaid one side of said fence by etching; removing said mask; anddepositing said operating layer partially over said seed and extendingtherefrom in said second direction.
 4. A method as in claim 3; furthercomprising removing a polycrystalline portion of the solidified regionof said seed layer after formation of said seed.
 5. A method as in claim1; wherein said seed layer and said operating layer are polysilicon. 6.A method as in claim 1; wherein said seed layer has a first thicknessand said molten region has a depth less than said first thickness andsaid operating layer has a second thickness and said molten zone has adepth less than said second thickness.
 7. A method as in claim 1;wherein said exposing step includes exposing a plurality of regions ofsaid seed layer to said beam to form a plurality of said seeds in saidseed layer.
 8. A method as in claim 1; wherein said seeds arerectangular with the longer side thereof in said first direction and arespaced apart in said second direction with said operating layertherebetween and said scanning is effected by moving a rectangular beamof electrons relative to said wafer with the longer side of the beamparallel to the longer side of said seeds.